After much faffing around, I’ve resubmitted my PCB order to JLCPCB and now I wait. I made a stack of changes around the edge connector pin-out arrangement to try and make the PCB track routing easier. After a couple of very long days, I managed to route the new CPU board, memory and LED output boards. Fingers crossed they work as expected. I just need to wait a couple of weeks for them to arrive now. The delay is due to factory shutdowns at JLCPCB but also shipping is really expensive, so I pick whatever is the cheapest option, and that can take a couple of weeks. However, I’m not in any real hurry as I’ve plenty to keep me busy.

Mia and I have been working hard on the CPU instruction set. I’ve never really designed an instruction set before and it’s a brilliant learning exercise. The decision to use a 16-bit data bus seems to have been a bit of a double-edged sword. On the one hand, you have a lot more room to store your instruction in, but, I get a pang of guilt when I have unused bits or even unused bytes in an instruction. Javelin doesn’t need to be short of physical memory as it can accommodate 16M-Words, but I don’t want to be wasting bytes all over the place.

Also, some of the instructions have a larger footprint than I would like, but on the flip-side, you can do a great deal with one instruction. Take the humble COPY instruction. It can be used to copy one register to another, registers to or from memory, constants into register or memory and in fact, all the functions you would expect for a COPY instruction. However, it can also execute a branch depending on the final value.

COPY R3, R2, NZ, JUMP, -16

This instruction copies the value from register R2 into register R3, then tests the value that was copied. If it’s NOT ZERO, a branch is executed back 16 addresses (branches are typically relative and not absolute).

Another variation would be:

COPY R3, R2, NZ, OSCALL, $ABCDEF

Basically it’s doing the same as the previous copy, but this time it’s called a system subroutine at absolute address $ABCDEF

Since the majority of the registers are 24-bits wide, you can do some other weird things like this:

COPY R3H, R2L

This will copy the lowest byte from register R2 over the top of the highest byte in register R3.

There are still some things that need to be worked out. You can copy to and from memory, but I need to work on the limitations of doing that and the syntax. It’s so easy to get carried away and before you know it, you have one instruction that can cook dinner and walk the dog.

There is one feature that I’m proud of as you can do this:

AND R4, R3, R2

This will AND the value in register R3 with the value in register R2 and place the result in register R4. You can also extend it with optional branching if required, like this:

AND R4, R3, R2, NZ, JUMP, -16

This is the current instruction list:

GROUP	GROUP Number	Function Number	Function
SYS	0 – 0000	0 – 0000	NOP
		1 – 0001	RET
		2 – 0010	IRET
		3 – 0011	TRAP
		4 – 0100	RND
STACK	1 – 0001	0 – 0000	POP
		1 – 0001	PUSH
BIT	2 – 0010	0 – 0000	BSET
		1 – 0001	BCLR
		2 – 0010	BNOT
SHIFT	3 – 0011	0 – 0000	SHFL
		1 – 0001	SHFR
		2 – 0010	ROL
		3 – 0011	ROR
		4 – 0100	ROLC
		5 – 0101	RORC
COUNT	4 – 0100	0 – 0000	INC
		1 – 0001	DEC
MATH	5 – 0101	0 – 0000	ADD
		1 – 0001	ADDC
		2 – 0010	SUB
		3 – 0011	SUBC
		4 – 0100	DIV
		5 – 0101	MUL
LOGIC	6 – 0110	0 – 0000	AND
		1 – 0001	NAND
		2 – 0010	OR
		3 – 0011	XOR
		4 – 0100	NOR
		5 – 0101	XNOR
		6 – 0110	NOT
		7 – 0111	NEG
		4th bit set indicates the function updates a destination register.
IO	7 – 0111	0 – 0000	IN
		1 – 0001	OUT
SWAP	8 – 1000	0 – 0000	SWAP
CMP	9 – 1001	0 – 0000	CMP
COPY	10- 1010	0 – 0000	COPY
	11-14		Not allocated
	15		RESERVED for extension instructions.

It’s a balancing act to try and get useful and powerful instructions, but reduce the number of memory transactions.

When the system eventually accommodates multiple CPU’s, I don’t mind if the CPU’s have to do more work to decode and execute complex instructions if that frees up the backplane, so another CPU can access memory.

As is often then case when you’ve not exactly sure what you’re doing, you think of brilliant ideas half-way through the project. I like the idea of being able to support a large memory address; 16M-words, and with the new memory card design which can accommodate 2M-words per board, it wouldn’t be too much of a torture to install 8 of these boards for the full 16M-word capacity. This did get me thinking though. Whilst having some global memory so multiple CPU’s can communicate with each other, share configuration data etc, maybe the idea of all memory being global is not the way forward.

If I return to my Nixdorf 8870 days, a system could have a maximum of 4 x CPU’s in a single system, and each CPU had 1Mb of internal memory. There was no global memory at all. At IPL, each CPU loaded it’s own configuration and user connections were assigned to a specific CPU. Each CPU having that internal memory meant that memory requests were not typically sent via the backplane. This may be something I need to look at in the future, especially if performance becomes an issue.

Anyway, for now I need to concentrate on getting the instruction set nailed down. Once that’s done, Mia and I can start on the assembler. Right now as I work my way through the instruction set creating examples, I’m hand encoding and it’s an error-prone torture. We’ve decided that the assembler will be built in VB.NET but will run as a command line program. You will pass it the source text file and the assembler will do all the hard work and output various logs and object files. This way we don’t have to waste a load of time crafting a pretty UI and all that stuff. All we will need to create and assemble programs in the beginning will be the assembler and Notepad.

More soon.